1. Field of the Invention
The present invention relates generally to the field of memory and memory controllers, and in particular to obtaining status information from memory modules.
2. Relevant Background
Memory modules, such as Dynamic Random Access Memory (DRAM) memory modules, enjoy widespread use in contemporary electronic devices. In typical applications, a memory controller manages one or more memory modules. Commonly, plural arrangements of memory modules form potentially large banks of working memory with desired binary word widths, e.g., x16, x32, etc. In such contexts, current and evolving memory standards provide efficient, high-performance signal and interface definitions governing the design and implementation of memory modules, such as packaged or non-packaged ICs.
As a non-limiting example, industry-standard memory specifications for Double Data Rate (DDR) Synchronous DRAMs (SDRAMs) appear in revision JSED79E of the “Double Data Rate (DDR) SDRAM Specification,” published by the JEDEC SOLID STATE TECHNOLOGY ASSOCIATION in May 2005. Related third-generation revisions of this standard are forthcoming. One may also refer to similar third generation standards for Graphics Double Data Rate (GDDR) memory modules.
Input/output signal definitions represent one standardization constraint of particular relevance when designers consider extending memory module functionality, or otherwise altering memory module operation. For example, as memory modules become increasingly sophisticated, they may require mode and other configuration settings information. Thus, it is now common for memory modules to include one or more mode registers, device identification registers, etc. Rather than requiring new signals and connections, the memory modules are configured to make these registers accessible to an associated memory controller via read/write operations that are similar to the read/write operations involving the stored data array(s) within the memory module.
For example, as taught in the co-pending priority applications identified earlier herein, it is known to incorporate a status register within a memory module that is readable by an associated memory controller. For example, the memory controller may retrieve status information from a memory module's status register by performing a synchronous read operation at a predefined memory address. As a non-limiting example, the status information may include temperature-related status information, such as refresh rate data identifying a temperature-dependent refresh rate period currently required by the memory module.